by Jan Marjanovic
on Wed 29 December 2021

I recently held a presentation at the 10th MicroTCA Workshop for Industry and Research, where I presented some hardware we have developed, discussed the advantages of using SoCs, and showed a couple of examples where we successfully leveraged the features of these devices.

At my day job the dataflow through …

Notes on "A Primer on Memory Consistency and Cache Coherence"

by Jan Marjanovic
on Thu 23 December 2021

Category: Books,

A Primer on Memory Consistency and Cache Coherence, Second Edition

Authors:

Vijay Nagarajan, University of Edinburgh
Daniel J. Sorin, Duke University
Mark D. Hill, University of Wisconsin, Madison
David A. Wood, University of Wisconsin, Madison

"This primer is intended for readers who have encountered memory consistency and cache coherence informally …

Stratix V accelerator card from eBay, part 8

by Jan Marjanovic
on Sun 31 October 2021

My last blog post on this topic explored the PCI Express connections on this board. I have determined that the board contains a custom FPGA with two Hard IPs for PCIe, where the commercially-available part only contains one. At the end of the post I explored different options on how …

Notes from Xilinx® Adapt 2021

by Jan Marjanovic
on Tue 07 September 2021

Xilinx Adapt 2021

Day 1 (2021-09-07)

Adaptive Computing: Innovation Accelerated [Ivo Bolsens (Xilinx)]

the hardware is adapted, rather the other way around
DSA
growing gap between the moore's law and AI requirements
requirements: 6G (100 Gbps, 0.1 ms latency)
Xilinx wants to be a platform company
Vivado/FPGA -> Vitis …

USB-to-UART cable from an old ISDN modem

by Jan Marjanovic
on Sat 31 July 2021

A short intermezzo from all FPGA-related stuff, this time we deal with an 8051-based USB device. This blog post describes how I converted an ISDN modem (with a USB connection) to a USB-to-UART cable.

During my vacation at my parents' house, I wanted to access the UART on the Ultra96 …

Notes from Chisel Community Conference China 2021

by Jan Marjanovic
on Sat 26 June 2021

Category: FPGA, Scala, Chisel,

Here are my notes from the Chisel Community Conference China 2021. The conference took place on June 26th 2021, and was organized as a hybrid conference, open to both on-site and remote participants (over Zoom). The organizers have promised that the recorded talks will be made available online in the …

Performance counters in Cache Coherent Interconnect in Zynq MPSoC

by Jan Marjanovic
on Sat 12 June 2021

In this blog post I describe my tinkering with the interconnect architecture of the Xilinx Zynq MPSoC. I specifically focus on the Performance Monitoring Unit (PMU) integrated into the Cache Coherence Interconnect (CCI).

I believe that most of the readers of my blog are already familiar with Xilinx Zynq® UltraScale …

Stratix V accelerator card from eBay, part 7

by Jan Marjanovic
on Sat 15 May 2021

The reverse engineering of the FPGA accelerator card from eBay is progressing well and documenting the DDR3 interface was a huge step forward. However, there is still one important part of the board which is not fully uncovered, the PCI Express® interface.

Hardware

Pikes Peak

Pikes Peak is a Stratix …

Stratix V accelerator card from eBay, part 6

by Jan Marjanovic
on Sun 28 February 2021

In my last blog post I have presented a method to extract the DDR3 pinout from the bitstream, obtained from the on-board Flash. In this post I will use the information obtained from the bitstream to instantiate a DDR3 memory controller and measure its performance.

DDR3 SDRAM Controller with UniPHY …

Stratix V accelerator card from eBay, part 5

by Jan Marjanovic
on Sun 10 January 2021

The last piece of the puzzle on the Stratix V board is the DDR3 memory pinout. Once this is figured out, I can finally start using the board for my developments. It is obvious that this is not the most simple way to get a cheap FPGA development board, but …

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