by Jan Marjanovic
on Sat 26 June 2021

Category: FPGA, Scala, Chisel,

Here are my notes from the Chisel Community Conference China 2021. The conference took place on June 26th 2021, and was organized as a hybrid conference, open to both on-site and remote participants (over Zoom). The organizers have promised that the recorded talks will be made available online in the …

New Ubuntu, old problems with ModelSim

by Jan Marjanovic
on Sat 20 April 2019

Category: FPGA, ModelSim,

A couple of days ago a new release of Ubuntu, Ubuntu 19.04 Disco Dingo was released. On my personal laptop I follow the non-LTS line, which brings me cool features and updated programs (e.g. Python 3.7, GCC 8.3, ...) out-of-the-box.

Unfortunately, because the libraries are updated, the …

Chisel tester with overridden step() method

by Jan Marjanovic
on Sun 14 October 2018

Category: FPGA, Scala, BFM,

Introduction

Chisel is a modern take on Hardware Description Languages, such as (System)Verilog and VHDL. Both Verilog and VHDL were conceived in 80s, and are currently still the main two options when it comes to describing hardware. From the Developer Experience point-of-view, I would say that both languages are …

Books read: E. Stavinov: 100 Power Tips for FPGA Designers

by Jan Marjanovic
on Tue 18 October 2016

Category: FPGA, Xilinx, Books,

I recently found a great book explaining in details FPGA workflow for Xilinx tools, titled 100 Power Tips for FPGA Designers. Evgeni Stavinov is an experienced FPGA designer who previously worked for Xilinx. It is not evident from the title, but this book focuses almost entirely on the Xilinx, while …

Debugging Linux start-up on Altera Cyclone V SoC with OpenOCD

by Jan Marjanovic
on Tue 12 July 2016

Category: FPGA, Altera, Linux, OpenOCD,

This blog post will show you how one can use the OpenOCD debugger with Altera Cyclone V SoC. Altera Cyclone V SoC is a very interesting integrated circuit, combining dual-core ARM processor and a decent FPGA, allowing a wide variety of possibilities to partition the application between the two.

Xilinx …

HDL data type for Python parser implementations

by Jan Marjanovic
on Sun 15 November 2015

Category: Python, Verilog, FPGA, HDL,

Recently I had to implement a parser for the PCIe protocol. The data was captured with Xilinx ChipScope and saved as TSV (tab-separated value) text file. I wanted to implement a parser in Python, my favorite language for this kind of tasks. I have stumbled to a problem when I …

Lattice iCE40 configuration using Raspberry Pi

by Jan Marjanovic
on Sun 18 January 2015

Category: Lattice, iCE40, FPGA, Raspberry Pi, bash,

As I mentioned in previous post, I started playing around with Lattice iCE40 FPGA. In the last post I did a quick overview of the iCE40 tools. The iCEcube2 cannot compete with Xilinx ISE and Altera Quartus II, not to mention the Vivado, but since this is a low-cost FPGA …

My first encounter with Lattice Semiconductor

by Jan Marjanovic
on Wed 24 December 2014

Category: Lattice, iCE40, FPGA,

The FPGA market is one of those classical markets where there are two players who have nearly 100% market share, e.g. PC processors (Intel and AMD), graphic cards (NVIDIA and ATI), ... The two mayor players on the FPGA market are Xilinx and Altera. Both of this two companies follows …

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